1. Field of the Invention
The present invention relates to a light emitting device. In particular, the present invention relates to a structure of an active matrix light emitting device having thin film transistors (hereafter referred to as TFTs) manufactured on an insulator such as glass or plastic. The present invention also relates to an electronic equipment using the light emitting device in its display portion.
2. Description of the Related Art
The development of display devices in which self light emitting elements such as electro luminescence (EL) elements are used, has been active recently. The term EL element includes either of an element that utilizes luminescence from a singlet exciton (fluorescence), and an element that utilizes luminescence from a triplet exciton (phosphorescence). An EL display device is given as an example of a light emitting device here, but display devices using other self light emitting elements are also included in the category of the light emitting device.
EL elements are composed of a light emitting layer sandwiched between a pair of electrodes (anode and cathode), normally a laminate structures. The laminate structure proposed by Tang et al. of Eastman Kodak Co. and having a hole transporting layer, a light emitting layer, and an electron transporting layer can be typically given. This structure has extremely high luminous efficiency, and this structure is applied to most EL elements that have been researched at present.
Further, other structures also exist, such as one in which a hole injecting layer, a hole transporting layer, a light emitting layer, and an electron transporting layer are laminated in sequence on an anode, and one in which a hole injecting layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injecting layer are laminated in sequence on an anode. Any of these structures may be adopted as an EL element structure in the present invention. Doping of fluorescent pigments or the like to the light emitting layer may also be performed.
All layers formed between an anode and a cathode are generically referred to as EL layers here. The aforementioned hole injecting layer, hole transporting layer, light emitting layer, electron transporting layer, and electron injecting layer are therefore all included in EL layers. A light emitting element structured by an anode, an EL layer, and a cathode is referred to as an EL element.
A schematic diagram of a light emitting device is shown in FIG. 3A. A pixel portion 301 is disposed in a center portion of a substrate 300. A source signal line driver circuit 302 for controlling source signal lines, and gate signal line driver circuits 303 for driving gate signal lines are disposed in the periphery of the pixel portion 301. The gate signal line driver circuits 303 are arranged symmetrically on both sides of the pixel portion 301 in FIG. 3A, but one of them may be placed on only one side. However, considering factors such as reliability and efficiency of circuit operation, it is preferable to dispose the gate signal line driver circuits 303 on both the sides.
Signals such as a clock signal, a start pulse, and an image signal are input to the source signal line driver circuit 302 and the gate signal line driver circuits 303 through a flexible printed circuit (FPC) or the like.
Operation of the driver circuits is explained. In the gate signal line driver circuit, pulses for selecting the gate signal lines are output one after another by a shift register 321 in accordance with the clock signal and the start pulse. Then, the voltage amplitude of the signals are transformed by a level shifter 322, and are output to the gate signal lines via a buffer 323, and a certain one row of the gate signal lines is placed in a selected state.
In the source signal line driver circuit, sampling pulses are output one after another by a shift register 311 in accordance with the clock signal and the start pulses. In a first latch circuit 312, storage of a digital image signal is performed in accordance with the timing of the sampling pulse. When operation for one horizontal period portion is completed, a latch pulse is input during a return period, and the digital image signals of one row portion stored in the first latch circuit 312 are transferred all at once to a second latch circuit 313. The digital image signals of one row portion are then written simultaneously to pixels of the row to which the pulse for selecting the gate signal line is output.
The pixel portion 301 is explained next. A portion shown by reference numeral 310 in the pixel portion 301 corresponds to one pixel, and the circuit structure of the pixel is shown in FIG. 3B. Reference numeral 351 in FIG. 3B denotes a TFT that functions as a switching element (hereafter referred to as a switching TFT) during writing of the image signal to the pixel. A TFT having either n-channel polarity or p-channel polarity may be used as the switching TFT 351. Reference numeral 352 denotes a TFV (hereafter referred to as a driver TFT) which functions as an element for controlling electric current supplied to an EL element 354. If the driver TFT 352 is an n-channel TFT, then one electrode 355 of the EL element 354 is taken as a cathode, and is connected to an output electrode of the driver TFT 352. The other electrode 356 of the EL element 354 therefore becomes an anode. On the other hand, if a p-channel TFT is used as the driver TFT 352, then the one electrode 355 of the EL element 354 is taken as an anode, and is connected to the output electrode of the driver TFT 352. The other electrode 356 of the EL element 354 therefore becomes a cathode. Reference numeral 353 denotes a storage capacitor (Cs) formed in order to store the electric potential applied to a gate electrode of the driver TFT 352. Although the storage capacitor (Cs) is shown here as an independent capacitive means, a capacitance that occurs between the gate electrode and a source region of the driver TFT 352, or a capacitance that occurs between the gate electrode and a drain region of the driver TFT 352 may also be utilized.
A simple explanation is given for the relationship between the polarity of the driver TFT 352 and the structure of the EL element 354, with reference to FIGS. 5A and 5B. FIG. 5A shows the structure of a pixel portion of an EL element, and FIG. 5B shows schematically the connections among a switching TFT 501, a driver TFT 502, and an EL element 504.
Further, TFT operation is discussed when explaining circuit operation in this specification. The term “TFT turns on” indicates that the absolute value of the voltage between a gate and a source of a TFT exceeds the absolute value of the TFT threshold voltage, and a source region and a drain region of the TFT are thus placed in a conductive state through a channel forming region. The term “TFT turns off” indicates that the absolute value of the voltage between the gate and the source of the TFT is lower than the absolute value of the TFT threshold voltage, and the source region and the drain region of the TFT are in a non-conductive state.
In addition, the terms “gate electrode, input electrode, output electrode” and gate electrode, source electrode, drain electrode” are used separately when explaining TFT connections. This is because the voltage between the gate and the source is often considered when explaining TFT operation, but it is difficult to clearly differentiate between the source region and the drain region of the TFT on a structural level. Therefore the two regions are referred to as the input electrode and the output electrode when explaining signal input and output, and one of the input electrode and the output electrode is referred to as the source region, while the other is referred to as the drain region, when explaining the relationship between the electric potentials of the TFT electrodes.
First, consider a case in which reference numeral 505 denotes an anode, and reference numeral 506 denotes a cathode in the EL element 504. If the electric potential of the electrode 505 is taken as V505 and the electric potential of the electrode 506 is taken as V506, then it is necessary to impart a forward bias between the anode and the cathode in order that the EL element 504 emits light. Therefore V505>V506 is satisfied. In order to turn on the driver TFT 502 with certainty if it is an n-channel TFT, and normally apply voltage between the electrodes of the EL element 504, it is necessary that the electric potential applied to the gate electrode of the driver TFT 502 be greater than V505 by at least the amount of the threshold value of the TFT 502. That is, it is necessary to expand the amplitude of a signal written in from a source signal line. On the other hand, it is necessary for the electric potential applied to the gate electrode of the driver TFT 502 be less than V505 by at least the amount of the threshold value of the TFT 502 in order to turn on the driver TFT 502 with certainty if it is a p-channel TFT and normally apply voltage between the electrodes of the EL element 504. It is therefore not necessary to expand the amplitude of the signal written in from the source signal line large amount. It is thus preferable to use a p-channel TFT for the driver TFT 502 for cases in which the electrode 505 is the anode, and the electrode 506 is the cathode in the EL element 504.
Further, if the driver TFT 502 is n-channel in this case, then a voltage VGS2 between the gate and the source of the driver TFT 502 becomes the voltage between the gate electrode of the driver TFT 502 and the anode 505 of the EL element 504, not that shown in FIG. 5B. If the resistance rises, increasing VEL, due to defects in the characteristics of the EL element 502 at this time, or due to long term degradation, then the electric potential of a source electrode of the driver TFT 502 increases. There is a possibility that the voltage between the gate and the source of the driver TFT 502 will cause dispersion to develop between pixels due to dispersion in EL elements 504. It is therefore preferable to use a p-channel TFT as the driver TFT 502 here.
In order to make the EL element 504 emit light when reference numeral 505 denotes the cathode, and reference numeral 506 denotes the anode in the EL element 504, it is necessary to impart an electric potential difference between both the electrodes. In this case, V505<V506 is satisfied. In order to turn on the driver TFT 502 with certainty if it is an n-channel TFT, and normally apply voltage between the electrodes of the EL element 504, the electric potential applied to the gate electrode of the driver TFT 502 is sufficiently greater than V505 by at least the amount of the threshold value of the TFT 502. It is therefore not necessary to expand the amplitude of the signal written in from the source signal line be a large amount. On the other hand, it is necessary for the electric potential applied to the gate electrode of the driver TFT 502 be made less than V505 by at least the amount of the threshold value of the TFT 502 in order to turn on the driver TFT 502 with certainty if it is a p-channel TFT and normally apply voltage between the electrodes of the EL element 504. That is, the amplitude of the signal written in from the source signal line must be expanded. It is thus preferable to use an n-channel TFT for the driver TFT 502 for cases in which the electrode 505 is the cathode, and the electrode 506 is the anode in the EL element 504.
Further, when considering the voltage between the gate and the source of the driver TFT 502, and the electric potential of the cathode of the EL element, it is also preferable to use a p-channel TFT for the driver TFT 502 in this case.
Next, the relationship between the direction of light emission to the polarity of the driver TFT 502 and the EL element 504 structure is discussed. FIG. 8A is a schematic cross sectional diagram of the structure of the EL element 504 when the driver TFT 502 is an n-channel TFT, and FIG. 8B is a schematic cross sectional diagram of the structure of the EL element 504 when the driver TFT 502 is a p-channel TFT.
It is preferable to use a metallic material in the cathode of the EL element 504 because the ability to inject electrons into a light emitting layer is desired. The electrode that uses a transparent electrode is therefore normally the anode. The driver TFT in FIG. 8A is therefore an n-channel TFT, a current supply line is connected to the source region of the driver TFT 502 and the cathode of the EL element 504 is connected to the drain region of the driver TFT 502. Consequently, light generated by the light emitting layer is emitted toward the transparent electrode anode side, and therefore the direction of light emission is opposite to a substrate on which the TFT is formed (hereafter referred to as a TFT substrate), as shown in the figure.
On the other hand, in FIG. 8B the driver TFT 502 is a p-channel TFT. The current supply line is connected to the source region of the driver TFT 502, and the anode of the EL element 504 is connected to the drain region of the driver TFT 502. Consequently, light generated by the light emitting layer is emitted toward the transparent electrode anode side, and therefore the direction of light emission is toward the TFT substrate, as shown in the figure.
The light emission direction shown in FIG. 8A is referred to as upper surface emission, and the light emission direction shown in FIG. 8B is referred to as lower surface emission here. The region occupied by the elements structuring the pixel portion influences the light emission surface area in the lower surface emission case. On the other hand, in the upper surface emission case, light can be extracted with no relation to the region occupied by the elements structuring the pixel portion, and this is useful in increasing the aperture ratio. However, it is necessary to form the anode using the transparent electrode after EL layer formation with process considerations when manufacturing an upper surface emission structure light emitting device, as shown in FIG. 8A. Damage is easily imparted to the EL layer by this process, and this type of process is difficult to be done at present. The lower surface emission structure shown in FIG. 8B is therefore generally employed.
A method of driving a light emitting device is explained next.
An analog gradation method and a digital gradation method can be given as examples of methods of expressing many gradations using a light emitting device. The analog gradation method is one in which electric current flowing in EL elements is controlled in an analog manner, thus controlling brightness, and gradations are obtained. However, minute dispersions in the characteristics of TFTs structuring a pixel portion have a large influence on dispersions in EL brightness. Namely, if there is dispersion in the characteristics of the driver TFT 102, then the amount of electric current flowing between a source and a drain of different driver TFTs will differ, even if the same electric potential is imparted to gate electrodes of the driver TFTs. In other words, dispersion in brightness develops due to the different amount of electric current flowing in the EL elements.
The digital gradation method is a method in which dispersion in the characteristics of the elements structuring the pixels does not easily influence image quality. The EL elements are driven by using only two states, an on state (a state in which the brightness is near 100%), and an off state (a state in which the brightness is nearly 0%). That is, it can be said that the digital gradation method is a driving method in which dispersion in the brightness of the EL elements is difficult to be distinguished even if there are dispersions in the amount of electric current flowing between the source and the drain of the driver TFTs.
However, only two gradations can be displayed with the digital gradation method in this state, and a plurality of techniques for achieving many gradations by combining the digital gradation method with another method have been proposed.
One method that can be given for achieving multiple gradations is a combination of the digital gradation method with a time gradation method. The term time gradation method denotes a method in which gradation expression is performed by controlling the amount of time during which the EL elements emit light. Specifically, one frame period is divided into a plurality of subframe periods of different lengths. Gradations are expressed by selecting whether or not the EL elements emit light during each subframe period, thus using the difference in length of time for light emission within one frame period.
The method disclosed in Japanese Patent Application Laid-open No. 2001-5426 is discussed here as one method of combining the digital gradation method with the time gradation method. A case of 3-bit gradation expression is explained here as an example.
Refer to FIGS. 9A to 9C. The frame frequency used in display devices such as liquid crystal displays and EL displays is normally on the order of 60 Hz. That is, screen drawing is performed on the order of 60 times per second, as shown in FIG. 9A. It is thus possible to perform display such that the human eye does not experience screen flicker. A period for performing screen drawing one time is referred to as one frame period here.
One frame period is divided into a plurality of subframe periods in a time gradation method disclosed in Japanese Patent Application Laid-open No. 2001-5426. The number of divisions at this point is equal to the number of gradation bits. Namely, one frame period is divided into three subframe periods SF1 to SF3 here because a 3-bit gradation is used.
In addition, each subframe period has an address (writing) period Ta and a sustain (light emission) period Ts. The address (writing) periods are periods for writing a digital image signal into pixels, and each subframe period has equal length. The sustain periods are periods during which the EL elements emit light based on the digital image signal written into the pixels during the address (writing) periods. Sustain (light emission) periods Ts1 to Ts3 have a length ratio that satisfies Ts1:Ts2:Ts3=4:2:1. That is, for n-bit gradation expression, n sustain (light emission) periods have a length ratio of 2n−1:2n−2: . . . :21:20. The length of the period for each pixel to emit light during one frame period is determined by the specific sustain (light emission) period during which the EL element emits light. Gradation expression is thus performed. In other words, by taking a light emitting state or a non-light emitting state for the sustain (light emission) periods Ts1 to Ts3 in FIG. 9B, and utilizing the length of the total light emission time, 8 gradations having brightnesses of 0%, 14%, 28%, 43%, 57%, 71%, 86%, and 100% can be expressed. The brightness is 57% if there is light emission during Ts1 and no light emission during Ts2 and Ts3, and while the brightness is 71%, light emission occurs during Ts1 and Ts3 but not during Ts2. To obtain a 71% brightness by an analog gradation method, control is performed by using a voltage corresponding to 71% brightness, and the 71% brightness is maintained over the entire one frame period. With the time gradation method, however, the same gradation is expressed by emitting light at 100% brightness for only 71% of the entire light emission period.
Operation is explained in detail. Continue to refer to FIGS. 9A to 9C, as well as FIG. 3B. First, the switching TFT 351 turns on when a selection pulse is input to a gate signal line. A digital image signal is input next from a source signal line, and control for whether the driver TFT 352 turns on or off is performed in accordance with the electric potential of the digital image signal. In addition, electric charge corresponding to the digital image signal is stored in the storage capacitor 353. Even if the driver TFT 352 turns on at this point, voltage is not applied between the anode (cathode) 355 and the cathode (anode) 356, and therefore light is not emitted. One such method is to set the electric potential of the cathode (anode) 356 equal to the electric potential of the anode (cathode) 355, namely to the electric potential of a current supply line (current). The cathode (anode) 356 is normally common across all pixels, and therefore this operation is performed simultaneously for all pixels.
At the point where writing operations are finished from a first row until a final row, the address (writing) period is complete, and all of the pixels move simultaneously into the sustain (light emission) period. Voltage is applied between the anode (cathode) 355 and the cathode (anode) 356 of the EL element 354, and electric current flows, causing light to be emitted.
One frame period is structured by performing the aforementioned operations over all of the subframe periods. To increase the number of display gradations with this method, the number of subframe periods may be increased. Further, it is not always necessary for the subframe periods to appear in order from the uppermost bit to the lowermost bit as shown in FIGS. 9B and 9C, and the subframe periods may be arranged randomly within the frame period. In addition, the order may also be changed within each frame period. This type of driving method is referred to as display period separated driving (DPS driving).
A lowered duty ratio (the period for performing gradation display, in which the pixels emit light, per frame period) can be given as one problem with DPS driving. The address (writing) period and the sustain (light emission) period are separated, and therefore periods exist within one frame period during which light is not emitted under any conditions. As a result, an overall drop in brightness can be perceived.
In a certain subframe period for pixels connected to a number m row gate signal line, writing of a digital image signal to the pixels is performed in a period 902 during which a gate signal line is selected, as shown in FIG. 9D, and light is emitted in a sustain (light emission) period 904. An address (writing) period is the total of periods denoted by reference numerals 901, 902, and 903 here. Reference numeral 901 denotes a period for performing writing of a digital image signal to the number 1 to the number (m−1) row, while reference numeral 903 denotes a period for performing writing of the digital image signal to the number (m+1) row to the final row. In other words, for the pixels connected to the number m row gate signal line, the periods denoted by reference numerals 901 and 903 in the address (writing) period become periods during which both writing and light emission are not performed, namely, “waiting” periods.
Address (writing) periods are formed in each of the subframe periods, and therefore the address (writing) periods also increase if many gradation levels are sought. There is also an increase in the aforementioned “waiting” periods, and this invites a further reduction in the duty ratio.
A method for solving these types of problems is given here. This method is one in which there is no separation between the address (writing) periods and the sustain (light emission) periods, as shown in FIG. 9E, and light emission begins immediately after writing of a digital image signal to pixels connected to a certain row gate signal line is complete. The pixels connected to the number m row gate signal line can be made to emit light also during the periods for performing writing of the digital image signal to the pixels connected to gate signal lines other than the number m row gate signal line, as shown in FIG. 9F, and therefore the problem of the reduction in the duty ratio can be solved with this method.
However, other problems develop with this method when considering the increase in the number of gradations.
FIGS. 10A and 10B are examples of dividing one frame period for a case of expressing 5-bit gradations by the above-mentioned DPS driving. The address (writing) periods increase accompanied with the increase in the number of divisions of the subframe periods, and the sustain periods are shorter compared to the 3-bit gradation case. It thus can be understood that the duty ratio is lower compared to the 3-bit gradation case. On the other hand, as shown in FIG. 10C, cases in which the duty ratio reduction is prevented by driving in accordance with a method in which the address (writing) periods and the sustain (light emission) periods are not separated are considered. The length ratio between sustain periods Ts1 to Ts5 of the respective subframe periods is Ts1:Ts2:Ts3:Ts4:Ts5=24:23:22:21:20=16:8:4:2:1.
Refer to FIG. 10B and focus on reference symbol SF5. It can be seen that the sustain (light emission) period is longer than the address (writing) period in SF5. Periods in which the address (writing) periods of different subframe periods overlap therefore develop for cases of driving in accordance with a driving method in which there is no separation between the address (writing) period and the sustain (light emission) period. Before writing to the final row is complete in SF5 in FIG. 10C, the sustain (light emission) period of the number 1 row has finished, and the next writing has started. In other words, the gate signal lines of two different rows are selected at the same time, and normal signal writing cannot be performed.
A display device shown in FIGS. 4A and 4B has been proposed in Japanese Patent Application No. 2000-86968 in order to solve this type of problem. The display device shown in FIG. 4A is nearly the same as the display device shown previously in FIG. 3A. The difference between the two is that the display device of FIG. 4A has a writing gate signal line driver circuit 403 and an erasure gate signal line driver circuit 404 on the left and right of a pixel portion 401.
The circuit structure of one pixel, denoted by reference numeral 410 in the display device of FIG. 4A, is shown in FIG. 4B. This structure differs from the pixel shown in FIG. 3B in that it has an erasure gate signal line and an erasure TFT 457.
The aforementioned problem in that different address (writing) period overlap is solved by using this type of display device.
An explanation is given regarding its operation. Refer to FIG. 4B and to FIGS. 10A to 10D for the explanation. First, a writing gate signal line is selected, and a switching TFT 451 turns on. A digital image signal is then input from a source signal line, a driver TFT 452 is controlled to turn on or off by the electric potential of the input signal, and in addition, an electric charge corresponding to the input signal is stored in a storage capacitor 453. Rows to which writing of the digital image signal is complete then move immediately to the sustain (light emission) period.
As shown in FIGS. 10C and 10D, an erasure period (Tr5) is formed after completion of the sustain (light emission) period for subframe periods having shorter sustain (light emission) periods than address (writing) periods. This is done so that the next address period does not begin immediately after the sustain (light emission) period. An EL element 454 does not emit light during the erasure period. The erasure TFT 457 turns on by the selection of the erasure gate signal line, releasing the electric charge stored in the storage capacitor 453, in the erasure period (Tr5). The electric current flowing in the driver TFT 452 thus stops, and the EL element 454 stops emitting light.
The length of the erasure period at this point becomes the length from after the address (writing) period for the number 1 row is complete until the address (writing) period for the final row is complete.
Multiple gradations are thus achieved by forming the erasure period to increase the duty ratio, and by preventing incorrect overlap of the address (writing) periods. In contrast to the DPS driving, this type of driving method is referred to as simultaneous erasing scan driving (SES driving).
Strictly speaking, the SES driving includes the meaning that writing and erasure are performed in parallel. In contrast to the DPS driving in which the address (writing) period and the sustain (light emission) period are separated, driving methods having no such separation are referred to as SES driving. Cases in which there is no specific erasure period are thus also included in the SES driving methods, as shown in FIGS. 9E and 9F.
The fact that manufacturing processes are complex for display devices manufactured by forming TFTs on an insulator invites a reduction in throughput and an increase in cost. The main challenge in reducing cost is therefore that process is simplified as much as possible. Structuring a pixel portion and peripheral driver circuits (such as a source signal line driver circuit and a gate signal line driver circuit) by using only TFTs of the same conductivity type is thus considered.
The operating voltages of the pixels and the driver circuits are once again considered. Refer again to FIGS. 5A and 5B. FIG. 5A shows the structure of an EL element pixel portion, and a schematic expression of connections among the switching TFT 501, the driver TFT 502 and the EL element 504 is shown in FIG. 5B.
If the driver TFT 502 is a p-channel TFT, then as discussed above, it is preferable that the electrode 505 of the EL element is the anode, and that the electrode 506 is the cathode. The polarity of the switching TFT 501 is considered with respect to the polarity of the driver TFT 502 here. First, for cases in which the driver TFT 502 is a p-channel TFT, the condition for the driver TFT 502 to turn on is that the absolute value of the gate-source voltage VGS2 of the driver TFT 502 is greater than the absolute value of the threshold voltage of the driver TFT 502. That is, the L level of the digital image signal input from the source signal line (the EL element is assumed to emit light when the electric potential of the digital image signal is L level here) is lower than the electric potential of the source region of the driver TFT 502 by more than the threshold value.
If the switching TFT 501 and the driver TFT 502 have the same polarity at this point, namely if they are both p-channel type, then the condition for the switching TFT 501 to turn on is that the absolute value of the gate-source voltage VGS1 of the switching TFT 501 is greater than the absolute value of the threshold voltage of the switching TFT 501. That is, the L level of a pulse that places the gate signal line in a selected state (the gate signal line is taken as being in a selected state when L level is input to the gate signal line because the switching TFT 501 is p-channel type here) is lower than the electric potential of the source region of the switching TFT 501 by more than the threshold value. It is therefore necessary for the voltage amplitude of the gate signal line side to be expanded with respect to the voltage amplitude of the source signal line. This means that the operating voltage of the gate signal line driver circuit is made higher.
Similar circumstances also exist if the switching TFT 501 and the driver TFT 502 are both n-channel TFTs. It therefore becomes preferable to use both n-channel and p-channel TFTs for the pixel portion TFTs when considering electric power consumption.
From the above discussion, although structuring the pixel portion and the driver circuits by TFTs of the same conductivity type in accordance with a conventional method achieves a reduction in the number of processes, it also invites an increase in electric power consumption.